As circuit fabrication technology scales, inter-die and intra-die variations in process parameters such as channel length, L, width, W, threshold voltage, Vt, and the like, have become serious problems in circuit design. For example, the device-to-device (intra-die) variations in L, W or Vt between neighboring transistors in a static random access memory (SRAM) cell can significantly degrade the stability of the cell and can result in read and write delays. The Vt of a field effect transistor (FET) of the p-type (PFET) may degrade due to a negative bias instability (NBTI) effect after burn-in, leading to problems with Vmin (the minimum voltage required to operate the memory cell) during READ and WRITE operations. If the PFET is made too strong (i.e., relatively high drain current iD for a given drain-source voltage differential VDS) the write margin may degrade significantly.
Accordingly, it would be desirable to address various issues arising in electronic circuit design, such as, for example, those arising in electronic circuits having several operating modes (e.g. a “READ” mode and a “WRITE” mode) as may be found in electronic memory circuits.